1. Field of the Invention
The invention relates to flash memories, and more particularly to data writing of flash memories.
2. Description of the Related Art
Flash memories are divided into single level cell (SLC) flash memories, multi level cell (MLC) flash memories, and triple level cell (TLC) flash memories. A memory cell of an SLC flash memory stores a single data bit. A single memory cell of an SLC flash memory is therefore capable of storing a data pattern of a single bit with a value equal to either 0 or 1. A memory cell of an MLC flash memory stores two data bits. A single memory cell of an MLC flash memory is therefore capable of storing data selected from four data patterns with bit values 00, 01, 10, and 11. A memory cell of a TLC flash memory stores three data bits. A single memory cell of a TLC flash memory is therefore capable of storing data selected from eight data patterns with bit values 000, 001, 010, 011, 100, 101, 110, and 111.
A voltage used to write data to a memory cell of a flash memory is referred to as a programming voltage. Different programming voltage values correspond to different data patterns written to a memory cell. For example, a programming voltage for programming memory cells of an SLC flash memory has two different programming voltage values, a programming voltage for programming memory cells of an MLC flash memory has four different programming voltage values, and a programming voltage for programming memory cells of a TLC flash memory has eight different programming voltage values. When a controller wants to write a data pattern to a memory cell of a flash memory, the flash memory sets the voltage level of the memory cell to be equal to the programming voltage values corresponding to the data pattern. When the controller requires the flash memory to read data from the memory cell, the flash memory measures the voltage level of the memory cell, and then compares the voltage level with the programming voltage values to determine which data pattern is stored in the memory cell.
Referring to FIG. 1, a schematic diagram of data programming of a memory cell of a TLC flash memory is shown. A single memory cell of the TLC flash memory stores three data bits including a least significant bit (LSB), a center significant bit (CSB), and an most significant bit (MSB). The flash memory sequentially writes the LSB, the CSB, and the MSB to a memory cell. First, when the LSB is written to the memory cell, the flash memory adjusts the programming voltage of the memory cell to the level 121 or the level 122 shown in FIG. 1 according to whether the value of the LSB is the bit 0 or bit 1. When the CSB is written to the memory cell, the flash memory then adjusts the programming voltage of the memory cell to the level 111, the level 112, the level 113, or the level 114 shown in FIG. 1 according to whether the value of the CSB is the bit 0 or bit 1, wherein the levels 111, 112, 113, and 144 indicate that the stored data content of the memory cell is respectively the bit pattern ‘11’, ‘01’, ‘00’, and ‘10’. When the MSB is finally written to the memory cell, the flash memory adjusts the programming voltage of the memory cell to the level 101, 102, 103, 104, 105, 106, 107, or 108 shown in FIG. 1 according to whether the value of the MSB is the bit 0 or bit 1, wherein the levels 101, 102, 103, 104, 105, 106, 107, and 108 indicate that the stored data content of the memory cell is respectively the bit pattern ‘111’, ‘011’, ‘001’, ‘101’, ‘100’, ‘000’, ‘010’, and ‘110’.
When a gap between the programming voltages corresponding to neighboring data patterns increases, the flash memory can easily identify the neighboring data patterns from each other. As shown in FIG. 1, the gaps between the neighboring programming voltage levels 101 and 102, 102 and 103, 103 and 104, 104 and 105, 105 and 106, 106 and 107, and 107 and 108 are roughly equal to each other. The data patterns corresponding to the neighboring programming voltages 101 and 102 are respectively ‘111’ and ‘011’, and the difference bit between the data patterns corresponding to the neighboring programming voltages 101 and 102 is therefore an MSB. The data patterns corresponding to the neighboring programming voltages 102 and 103 are respectively ‘011’ and ‘001’, and the difference bit between the data patterns corresponding to the neighboring programming voltages 102 and 103 is therefore a CSB. The data patterns corresponding to the neighboring programming voltages 103 and 104 are respectively ‘001’ and ‘101’, and the difference bit between the data patterns corresponding to the neighboring programming voltages 103 and 104 is therefore an MSB. Similarly, the difference bit between the data patterns corresponding to the neighboring programming voltages 104 and 105, 105 and 106, 106 and 107, and 107 and 108 are therefore respectively an LSB, an MSB, a CSB, and an MSB. Thus, the difference bit has a higher probability to be an MSB, a medium probability to be a CSB, and a lower probability to be an LSB. When a plurality of memory cells of a flash memory are equally programmed according to the programming voltages 101, 102, 103, 104, 105, 106, 107, and 108, an MSB therefore has the highest amount of error rate occurrences, a CSB therefore has a medium amount of error rate occurrences, and an LSB therefore has the lowest amount of error rate occurrences. Because the MSB is more significant than the CSB and the LSB, if the MSB has a higher amount of error rate occurrences than those of the CSB and the LSB according to the conventional programming voltage shown in FIG. 1, resulting errors would have a greater impact on data written to a flash memory according to the conventional programming voltages. Thus, a data writing method is required to lower the error rate of an MSB of data written to a flash memory, thereby improving the performance of a data storage device.